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Verilog Code Generation
1 paper across 1 session
Poster Session 1
1 paper
Wednesday, December 3, 2025 · 11:00 AM → 2:00 PM
Exhibit Hall C,D,E
QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
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#1904
·
Yang Zhang, Rui Zhang, Jiaming Guo, Huang Lei, Di Huang, Yunpu Zhao, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen
