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Timing
1 paper across 1 session
Poster Session 1
1 paper
Wednesday, December 3, 2025 · 11:00 AM → 2:00 PM
Exhibit Hall C,D,E
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
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#1502
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Raghu Vamshi Hemadri, Jitendra Bhandari, Andre Nakkab, Johann Knechtel, Badri Gopalan, Ramesh Narayanaswamy, Ramesh Karri, Siddharth Garg
